r07ds1066ej0100 rev.1.00 page 1 of 7 may 10, 2013 preliminary datasheet RJF0609JSP 60v - 1.5v silicon n channel thermal fet power switching description this fet has the over temperature shut-down capability sensin g to the junction temperature. this fet has the built-in over temperature shut-down circuit in the gate area. and this circuit operation to shut-down the gate voltage in case of high junction temperature like applying over power consumption, over current etc.. features ? logic level operation (4 v gate drive). ? built-in the over temperature shut-down circuit. ? high endurance capability against to the short circuit. ? latch type shut down operation (need 0 voltage recovery). ? built-in the current limitation circuit. ? high density mounting ? power supply voltage applies 12 v and 24 v. ? aec-q101 compliant outline 1 2 3 4 5 6 7 8 1, 3 source 2, 4 gate 5, 6, 7, 8 drain renesas package code: prsp0008dd-d (package name: sop-8 (fp-8dav)) mos1 2 1 78 gate resistor temperature sensing circuit latch circuit gate shut-down circuit current limitation circuit mos2 4 3 56 gate resistor temperature sensing circuit latch circuit gate shut-down circuit current limitation circuit absolute maximum ratings (ta = 25c) item symbol ratings unit drain to source voltage v dss 60 v gate to source voltage v gss 16 v gate to source voltage v gss ?2.5 v drain current i d note4 1.5 a body-drain diode reverse drain current i dr 1.5 a avalanche current i ap note 3 1.5 a avalanche energy e ar note 3 9.6 mj channel dissipation pch note 1 1 w channel dissipation pch note 2 1.5 w channel temperature tch 150 c storage temperature tstg ?55 to +150 c notes: 1. 1 drive operation : when using the glass epoxy board (fr4 40 40 1.6 mm), pw 10 s 2. 2 drive operation : when usin g the glass epoxy board (fr4 40 40 1.6 mm), pw 10 s 3. tch = 25 c, rg 50 4. it provides by the current limitation lower bound value. r07ds1066ej0100 rev.1.00 may 10, 2013
RJF0609JSP preliminary r07ds1066ej0100 rev.1.00 page 2 of 7 may 10, 2013 typical operation characteristics (ta = 25c) item symbol min typ max unit test conditions input voltage v ih 3.5 ? ? v v il ? ? 1.2 v input current (gate non shut down) i ih1 ? ? 100 a vi = 8 v, v ds = 0 i ih2 ? ? 50 a vi = 3.5 v, v ds = 0 i il ? ? 1 a vi = 1.2 v, v ds = 0 input current (gate shut down) i ih(sd)1 ? 0.8 ? ma vi = 8 v, v ds = 0 i ih(sd)2 ? 0.35 ? ma vi = 3.5 v, v ds = 0 shut down temperature tsd ? 175 ? c channel temperature gate operation voltage vop 3.5 ? 12 v drain current (current limitation value) i d limt 1.5 ? ? a v gs = 5 v, v ds = 10 v note 5 notes: 5. pulse test electrical characteristics (ta = 25c) item symbol min typ max unit test conditions drain current i d1 ? ? 5.4 a v gs = 3.5 v, v ds = 10 v note 6 i d2 ? ? 10 ma v gs = 1.2 v, v ds = 10 v i d3 1.5 ? ? a v gs = 12 v, v ds = 10 v note 6 drain to source breakdown voltage v (br)dss 60 ? ? v i d = 10 ma, v gs = 0 gate to source breakdown voltage v (br)gss 16 ? ? v i g = 800 a, v ds = 0 v (br)gss ?2.5 ? ? v i g = ?100 a, v ds = 0 gate to source leak current i gss1 ? ? 100 a v gs = 8 v, v ds = 0 i gss2 ? ? 50 a v gs = 3.5 v, v ds = 0 i gss3 ? ? 1 a v gs = 1.2 v, v ds = 0 i gss4 ? ? ?100 a v gs =? 2.4 v, v ds = 0 input current (shut down) i gs(op)1 ? 0.8 ? ma v gs = 8 v, v ds = 0 i gs(op)2 ? 0.35 ? ma v gs = 3.5 v, v ds = 0 zero gate voltage drain current i dss ? ? 10 a v ds = 32 v, v gs = 0 ta = 125 c gate to source cutoff voltage v gs(off) 1.1 ? 2.1 v i d = 1 ma, v ds = ?0 v forward transfer admittance |y fs | 1.0 2.2 ? s i d = 0.7 a, v ds = 10 v note 6 static drain to source on state resistance r ds(on) ? 208 350 m i d = 0.7 a, v gs = 4 v note 6 r ds(on) ? 142 263 m i d = 0.7 a, v gs = 10 v note 6 output capacitance coss ? 265 ? pf v ds = 10 v, v gs = 0, f = 1mhz turn-on delay time t d(on) ? 0.55 ? s i d = 0.7 a, v gs = 10 v rise time t r ? 1.88 ? s r l = 43 turn-off delay time t d(off) ? 3.9 ? s fall time t f ? 3.7 ? s body-drain diode forward voltage v df ? 0.82 ? v i f = 1.5 a, v gs = 0 body-drain diode reverse recovery time t rr ? 71 ? ns i f = 1.5 a, v gs = 0 di f /dt = 50 a/ s over load shut down operation time note 7 t os1 ? 1.02 ? ms v gs = 5 v, v dd = 16 v t os2 ? 0.59 ? ms v gs = 5 v, v dd = 24 v notes: 6. pulse test 7. including the junction temperature rise of the over loaded condition.
RJF0609JSP preliminary r07ds1066ej0100 rev.1.00 page 3 of 7 may 10, 2013 main characteristics 10 1 110 100 5 2 4 3 1 08 246 10 100 0.1 0.01 0.1 0.1 1 10 10 1000 100 pw = 1 ms 10 ms v gs = 4 v 10 v v gs = 3.5 v 4 v 300 200 100 0 0246810 i d = 0.25 a 0.5 a 0.75 a 1.5 1.0 0.5 0 0 123 5 4 v ds = 10 v pulse test tc = 150c 25c ?40c 4.0 3.0 2.0 1.0 0 0 50 100 150 200 5 v 6 v 8 v 10 v drain to source voltage v ds (v) drain current i d (a) maximum safe operation area drain to source voltage v ds (v) drain source saturation voltage vs. gate to source voltage drain current i d (a) typical output characteristics drain current i d (a) static drain to source on state resistance vs. drain current pulse test pulse test pulse test gate to source voltage v gs (v) gate to source voltage v gs (v) drain current i d (a) typical transfer characteristics channel dissipation pch (w) ambient temperature ta (c) power vs. temperature derating dc operation pw 10s note8 thermal shut down operation area operation in this area is limited r ds(on) drain to source saturation voltage v ds(on) (mv) static drain to source on state resistance r ds(on) (m) ta = 25c 1 shot pulse 1 driver operation 1 driver operation 2 driver operation note 8: when using the glass epoxy board. (fr4 40 x 40 x 1.6 mm) test condition. when using the glass epoxy board. (fr4 40 x 40 x 1.6 mm), (pw 10s)
RJF0609JSP preliminary r07ds1066ej0100 rev.1.00 page 4 of 7 may 10, 2013 0 0.2 0.6 0.8 1.0 0.4 1.2 2.0 1.5 1.0 0.5 01020 40 60 50 30 10000 1000 100 10 v gs = 0 f = 1 mhz coss 0.1 1 10 100 1000 10 di / dt = 50 a / s v gs = 0 0.1 1 10 1 0.1 10 v gs = 10 v, v dd = 30 v pw = 300 s, duty 1 % t f t d(off) t d(on) t r 400 300 ?50 ? 25 0 25 50 75 100 125 150 0 100 200 v gs = 4 v i d = 0.25 a, 0.5 a, 0.75 a i d = 0.25 a, 0.5 a, 0.75 a 10 v v gs = 0 v 5 v 2 4 16 12 14 10 8 6 0 10 0.1 1 v dd = 16 v 24 v source to drain voltage v sd (v) reverse drain current vs. source to drain voltage reverse drain current i dr (a) capacitance c (pf) drain to source voltage v ds (v) typical capacitance vs. drain to source voltage reverse drain current i dr (a) reverse recovery time t rr (ns) body-drain diode reverse recovery time drain current i d (a) switching time t ( s) switching characteristics pulse test case temperature tc (c) static drain to source on state resistance vs. temperature pulse test gate to source voltage v gs (v) gate to source voltage vs. shutdown time of load-short test shutdown time of load-short test pw (ms) static drain to source on state resistance r ds(on) (m)
RJF0609JSP preliminary r07ds1066ej0100 rev.1.00 page 5 of 7 may 10, 2013 200 180 160 140 120 0 100 246 810 i d = 0.2 a 10 100 1 m 10 m 100 m 1 10 100 1000 10000 10 1 0.1 0.01 0.001 0.0001 d = 1 0.5 0.2 0.1 0.05 0.02 0.01 1shot pulse dm p pw t d = pw t ch-f(t) = s (t) ch - f ch-f = 125c/w, ta = 25 c when using the glass epoxy board (fr4 40 x 40 x 1.6 mm) 10 100 1 m 10 m 100 m 1 10 100 1000 10000 10 1 0.1 0.01 0.001 0.0001 d = 1 0.5 0.2 0.1 0.05 0.02 0.01 1shot pulse dm p pw t d = pw t ch-f(t) = s (t) ch - f ch-f = 166c/w, ta = 25 c when using the glass epoxy board (fr4 40 x 40 x 1.6 mm) 0.1 1 10 10 1 0.1 forward transfer admittance vs. drain current 25c ta = C40c 150c forward transfer admittance |y fs | (s) drain current i d (a) v ds = 10 v pulse test gate to source voltage v gs (v) shutdown case temperature tc ( c) shutdown case temperature vs. gate to source voltage pulse width pw (s) normalized transient thermal impedance s (t) normalized transient thermal impedance vs. pulse width (1 drive operation) pulse width pw (s) normalized transient thermal impedance s (t) normalized transient thermal impedance vs. pulse width (operatioon of 2 devices; allowable value per device)
RJF0609JSP preliminary r07ds1066ej0100 rev.1.00 page 6 of 7 may 10, 2013 d. u. t rg i ap monitor v ds monitor v dd 50 vin 10 v 0 i d v ds i ap v (br)dss l v dd e ar = l ? i ap 2 ? 2 1 v (br)dss v (br)dss C v dd avalanche test circuit avalanche waveform vin monitor d.u.t. vin 10v r l v dd = 30 v t r t d(on) vin 90% 90% 10% 10% vout t d(off) vout monitor 50 90% 10% t f switching time test circuit waveform
RJF0609JSP preliminary r07ds1066ej0100 rev.1.00 page 7 of 7 may 10, 2013 package dimensions p-sop8-3.95 x 4.9-1.27 0.085g mass[typ.] fp-8dav prsp0008dd-d renesas code jeita package code previous code a 8 5 1 4 f b p c detail f terminal cross section 1.27 1.08 0.40 l 1 0.60 0.25 x 0.460.400.34 0.10 b p b 1 c 1 0.250.200.15 maxnommin dimension in millimeters symbol reference 5.3 4.90 d 3.95 e 0.14 a 2 6.206.105.80 0.25 1.75 a 0.75 z l 8 0 c 1.27 e 0.1 y h e a 1 d * 1 * 2 e h e * 3 x m b p e z (ni/pd/au plating) 2. 1. dimensions "*1(nom)" and "*2" do not include mold flash. note) dimension "*3" does not include trim offset. index mark a 1 l 1 l detail f y package name sop-8 ordering information orderable part number quan tity shipping container RJF0609JSP-00-j0 2500 pcs/reel taping note: the symbol of 2nd "-" is occasionally presented as "#".
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